1. Field of the Invention
The present inventive concept relates to a nonvolatile memory device, and more particularly to a nonvolatile memory device having a structure requiring a reduced number of processing steps, and a method of manufacturing the same.
2. Description of the Prior Art
Nonvolatile memory devices retain stored information even though the external power supply to the device is interrupted. An example of such a nonvolatile memory is an EEPROM (Electrically Erasable Programmable Read Only Memory). In an EEPROM device, charge is stored in a floating gate after passing through a thin insulating layer, i.e., a tunnel oxide layer, comprising an insulating material such as SiO2, by a Fowler-Nordheim tunneling phenomenon. A transistor is turned on or off depending upon the amount of the stored charge.
Types of EEPROM devices include a 1-transistor type memory device and a 2-transistor type memory device. In a 1-transistor type memory device, data can be erased from the device in units of blocks. In a 2-transistor type memory device, data can be erased from the device in units of bytes. In the 1-transistor type EEPROM, a unit memory cell includes a memory transistor for storing data. In the 2-transistor type EEPROM, a unit memory cell includes a select transistor for selecting a cell and a memory transistor for storing data.
The memory transistor typically includes a floating gate separated by unit cells to store charge, and a control gate connected between unit cells to be used as one line, i.e., a sense line, and receiving a predetermined voltage for programming and/or erasing.
Since the structure of the memory transistor includes floating gate and a control gate, a photo etching process is required at least twice to form a gate of the memory transistor. That is, the gate of the memory transistor is formed through a series of processes including a first conduction layer forming process for the floating gate, a primary photo etching process with respect to the first conduction layer for separating the floating gate by unit cells, an inter-gate insulating layer forming process, a second conduction layer forming process for the control gate, and a secondary photo etching process with respect to the second conduction layer, the inter-gate insulating layer, and the first conduction layer. The primary and secondary photo etching processes are required.
Since the photo etching process is required at least twice in forming the gate of the memory transistor, processing time and processing cost increase.